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CY28401
100-MHz Differential Buffer for PCI Express and SATA
Features
* CK409 or CK410 companion buffer * Eight differential 0.7V clock pairs * Individual OE controls * Low CTC jitter (< 50 ps) * Programmable bandwidth * SRC_STOP# power management control * SMBus Block/Byte/Word Read and Write support * 3.3V operation * PLL Bypass-configurable * Divide by 2 programmable * 48-pin SSOP package
Functional Description
The CY28401 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
Pin Configuration
SRC_DIV2# VDD VSS SRCT_IN SRCC_IN OE_0 OE_3 DIFT0 DIFCO VSS VDD DIFT1 DIFC1 OE_1 OE_2 DIFT2 DIFC2 VSS VDD DIFT3 DIFC3 PLL/BYPASS# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD_A VSS_A IREF LOCK OE_7 OE_4 DIFT7 DIFC7 VSS VDD DIFT6 DIFC6 OE_6 OE_5 DIFT5 DIFC5 VSS VDD DIFT4 DIFC4 HIGH_BW# SRC_STOP# PWRDWN# VSS
DIFT0 OE_[0:7] SRC_STOP# PWRDWN#
Output Control
DIFC0 DIFT1 DIFC1 DIFT2
SCLK SDATA SRC_DIV2# PLL/BYPASS# SRCT_IN SRCC_IN
SMBus Controller Output Buffer
DIFC2 DIFT3 DIFC3 DIFT4 DIFC4 DIFT5 DIFC5
CY28401
DIV
HIGH_BW#
DIFT6 DIFC6
PLL
48 SSOP
DIFT7 DIFC7 LOCK
Cypress Semiconductor Corporation Document #: 38-07592 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised July 14, 2005
CY28401
Pin Description
Pin 4,5 Name SRCT_IN, SRCC_IN Type I,DIF Description 0.7V Differential SRC inputs from the clock synthesizer
8,9,12,13,16,17,20,21,29,30, DIFT/C(7:0) 33,34,37,38,41,42 6,7,14,15,35,36,43,44 28 45 26 1 27 23 24 46 22 48 47 3,10,18,25,32,40 2,11,19,31,39 OE_(7:0) HIGH_BW# LOCK PWRDWN# SRC_DIV/2# SRC_STOP# SCLK SDATA IREF PLL/BYPASS# VDD_A VSS_A VSS VDD
O,DIF 0.7V Differential Clock Outputs I,SE I,SE O,SE I,SE I,SE I,SE I,SE I I 3.3V GND I I 3.3V LVTTL active LOW input for three-stating differential outputs 3.3V LVTTL input for selecting PLL bandwidth 3.3V LVTTL output, transitions high when PL lock is achieved (latched output) 3.3V LVTTL input for Power-down, active LOW 3.3V LVTTL input for selecting input frequency divided by two, active LOW 3.3V LVTTL input for SRC_Stop#, active LOW SMBus Slave Clock Input A precision resistor is attached to this pin to set the differential output current 3.3V LVTTL input for selecting fan-out or PLL operation 3.3V Power Supply for PLL Ground for PLL Ground for outputs 3.3V power supply for outputs
I/O,OC Open collector SMBus data
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Description
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 Start Slave address - 7 bits Write = 0 Description Bit 1 2:8 9 Start Slave address - 7 bits Write = 0 Block Read Protocol Description
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CY28401
Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Description Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count from master - 8 bits Acknowledge from slave Data byte 0 from master - 8 bits Acknowledge from slave Data byte 1 from master - 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data Byte N - 8 bits Acknowledge from slave Stop Bit 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description Block Read Protocol Description Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from host Data byte 0 from slave - 8 bits Acknowledge from host Data byte 1 from slave - 8 bits Acknowledge from host Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Acknowledge from host Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Byte 0: Control Register 0 Bit 7 6 @pup 0 0 Name Description PWRDWN# drive mode 0 = Driven when stopped, 1 = Three-state SRC_STOP# drive mode 0 = Driven when stopped, 1 = Three-state
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CY28401
Byte 0: Control Register 0 (continued) Bit 5 4 3 2 1 0 @pup 0 0 0 1 1 1 Name Reserved Reserved Reserved HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth PLL/Bypass# 0 = Fanout buffer, 1 = PLL mode SRC_DIV/2 0 = Divided by 2 mode, 1 = Normal (output = input) Description
Byte 1: Control Register 1 Bit 7 @pup 1 Name DIF_7 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_6 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_5 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_4 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_3 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_2 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_1 Output Enable 0 = Disabled (three-state) 1 = Enabled DIF_0 Output Enable 0 = Disabled (three-state) 1 = Enabled Description
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Byte 2: Control Register 2 Bit 7 @pup 0 Name Description Allow Control DIF_7 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_6 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_5 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_4 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP#
6
0
5
0
4
0
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CY28401
Byte 2: Control Register 2 (continued) Bit 3 @pup 0 Name Description Allow Control DIF_3 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_2 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_1 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP# Allow Control DIF_0 with assertion of SRC_STOP# 0 = Free-running 1 = Stopped with SRC_STOP#
2
0
1
0
0
0
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 4: Vendor ID Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
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CY28401
PWRDWN# Clarification[1]
The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN# is an asynchronous input for powering up the system. When PWRDWN# is asserted LOW, all clocks will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and must meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnormalities among others. three-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC HIGH-to-LOW transition. When the SMBus power-down drive mode bit is programmed to `0', all clock outputs will be held with the DIFT pin driven high at 2 x Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to `1', then both DIFT and the DIFC are three-stated.
PWRDWN# Deassertion
The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN# pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable clocks are output from the buffer chip (PLL locked). If the control register PWRDWN# three-state bit is programmed to `1', all differential outputs must be driven high in less than 300 s of PWRDWN# deassertion to a voltage greater than 200 mV.
PWRDWN# Assertion
When PWRDWN# is sampled LOW by two consecutive rising edges of DIFC, all DIFT outputs will be held HIGH or
PWRDWN# DIFT DIFC
Figure 1. PWRDWN# Assertion Diagram
Tstable <1mS
PWRDWN# DIFT DIFC
Tdrive_Pwrdwn# <300uS, >200mV
Figure 2. PWRDWN# Deassertion Diagram Table 4. Buffer Power-up State Machine State 0 1 2[5] 3[2,3,4] 3.3V Buffer power off After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms-0.3-ms delay Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation Description
Notes: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. 2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input). 3. Lock output is a latched signal that is reset with the assertion of PWRDWN# or when VDD < 1.8V, 4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e., overshoot undershoot is allowed). 5. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled.
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CY28401
No Input Clock
S2 S1
Delay >0.25ms
Wait for Input Clock & PWRDWN# Deassertion
PWRDWN# Asserted
S0
Power Off
S3
Normal Operation
Figure 3. Buffer Power-up State Diagram
SRC_STOP# Clarification
The SRC_STOP# signal is an active LOW input used for clean stopping and starting the DIFT/C outputs (valid clock must be present on SRCT/C_IN). The SRC_STOP# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) Table 5. SRC_STOP# Functionality[6] SRC_STOP# 1 0 DIFT Normal Iref * 6 or Float DIFC Normal Low
transition. When the control register SRC_STOP# three-state bit is programmed to `0', the final state of all stopped DIFT/C signals is DIFT clock = HIGH and DIFC = LOW. There will be no change to the output drive current values, DIFT will be driven HIGH with a current value equal 6 x Iref, and DIFC will not be driven. When the control register SRC_STOP# three-state bit is programmed to `1', the final state of all stopped DIF signals is LOW, both DIFT clock and DIFC clock outputs will not be driven.
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2-6 DIFT/C clock periods (2 clocks are shown) with all DIFT/C outputs resuming simultaneously. If the control register three-state bit is programmed to `1' (three-state), then all stopped DIFT outputs will be driven high within 10 ns of SRC_STOP# deassertion to a voltage greater than 200 mV.
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is that all DIF outputs that are set in the control registers to stoppable via assertion of SRC_STOP# are stopped after their next
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
Note: 6. In the case where OE is asserted LOW, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.
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CY28401
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 6. SRC_STOP# =Three-state, PWRDWN# = Driven
1mS SRC_STOP# PWRDWN# DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable)
Figure 7. SRC_STOP# =Three-state, PWRDWN# = Three-state
Output Enable Clarification
The OE function may be implemented in two ways, via writing a `0' to SMBus register bit corresponding to output of interest or by asserting an OE input pin LOW. In both methods, if SMBus registered bit has been written LOW or the OE pin is LOW or both, the output of interest will be three-stated. (The assertion and deassertion of this signal is absolutely asynchronous.) Table 6. OE Functionality OE (Pin)# 1 1 0 0 OE (SMBus Bit) 1 0 1 0 DIFT Normal Three-state Three-state Three-state DIFC Normal Low Low Low
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CY28401
OE Assertion (Transition from `0' to `1')
All differential outputs that were three-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2-6 DIF clock periods. In addition, DIFT clocks will be driven HIGH within 10 ns of OE assertion to a voltage greater than 200 mV. function may be implemented in two ways, via writing a `0' to SMBus register bit or by asserting the SRC_DIV2# input pin LOW. In both methods, if the SMBus register bit has been written LOW or the SRC_DIV2# pin is LOW or both, all DIF outputs will configured for divide by 2 operation.
SRC_DIV2# Assertion
The impact of asserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from normal operation (output frequency equal to input) to half the input frequency within 2-6 DIF clock periods.
OE Deassertion (Transition from `1' to `0')
The impact of deasserting OE is each corresponding output will transition from normal operation to three-state in a glitch-free manner. The maximum latency from the deassertion to three-stated outputs is between 2-6 DIF clock periods.
SRC_DIV2# Deassertion
The impact of deasserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from divide by 2 mode to normal (output frequency is equal to the input frequency) operation within 2-6 DIF clock periods.
LOCK Signal Clarification
The LOCK output signal is intended to provide designers a signal indicating that PLL lock has been achieved and valid clock are available. This can be helpful when cascading multiple buffers that each contribute a 1-ms start-up delay in addition to the start-up time of the clock source. Upon receiving a valid clock on the SRC_IN input (PWRDWN# deasserted), the buffer will begin ramping the internal PLL until lock is achieved and stable, the clock buffer will assert the LOCK pin HIGH and enable DIF output clocks. In other words, if power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, all DIF clocks remain disabled. Only after valid input clocks are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are LOCK to be asserted and the DIF outputs enabled. The maximum start-up latency from valid clocks on SRC_IN input to the assertion of LOCK (output clocks are valid) is to be less than 1 ms. Once LOCK has been asserted high, it will remain high (regardless of the actual PLL status) until power is removed or the PWRDWN# pin has been asserted.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass mode (no PLL) and PLL mode. In bypass mode, the input clock is passed directly to the output stage resulting in 50-ps additive jitter (50 ps + input jitter) on DIF outputs. In the case of PLL mode, the input clock is pass through a PLL to reduce high-frequency jitter. The BYPASS# mode may be selected in two ways, via writing a `0' to SMBus register bit or by asserting the PLL/BYPASS# pin LOW. In both methods, if the SMBus register bit has been written LOW or PLL/BYPASS# pin is LOW or both, the device will be configured for BYPASS operation.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This mode is intended to minimize PLL peaking when two or more buffers are cascaded by staggering device bandwidths. The PLL low-bandwidth mode may be selected in two ways, via writing a `0' to SMBus register bit or by asserting the HIGH_BW# pin is LOW or both; the device will be configured for low-bandwidth operation.
SRC_DIV2# Clarification
The SRC_DIV2# input is used to configure the DIF output mode to be equal to the SRC_IN input frequency or half the input frequency in a glitch-free manner. The SRC_DIV2#
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CY28401
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to V SS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. 2000 V-0 1 Condition Min. -0.5 -0.5 -0.5 -65 0 Max. 4.6 4.6 VDD + 0.5 +150 70 150 TBD TBD Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD_A, VDD VILI2C VIHI2C VIL VIH VOL VOH IIL IIH IOZ CIN COUT LIN IDD3.3V IPD3.3V IPD3.3V Description 3.3V Operating Voltage Input Low Voltage Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage 3.3V Output Low Voltage 3.3V Output High Voltage Input Low Leakage Current Input High Leakage Current High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max. load and 100 MHz PD asserted, Outputs driven PD asserted, Outputs Three-stated IOL = 1 mA IOH = -1 mA Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD -10 2 3 - - - - 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.5 2.0 - 2.4 -5 5 10 5 6 7 300 65 5 Max. 3.465 1.0 - 0.8 VDD + 0.5 0.4 - Unit V V V V V V V A A A pF pF nH mA mA mA
AC Electrical Specifications
Parameter Description Condition Measured at crossing point VOX Measured at crossing point VOX at 100 MHz Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. 45 - 9.9970 - 175 - - - Measured SE 660 Max. 55 200 10.0533 50 700 20 125 125 850 Unit % ps ns ps ps % ps ps mv DIF at 0.7V TDC DIFT and DIFC Duty Cycle TSKEW TPERIOD TCCJ TR / TF TRFM TR TF VHIGH Average Period DIFT/C Cycle to Cycle Jitter DIFT and DIFC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High
Any DIFT/C to DIFT/C Clock Skew, SSC Measured at crossing point VOX
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CY28401
AC Electrical Specifications (continued)
Parameter VLOW VOX VOX VOVS VUDS VRB tPD(PLL) Voltage Low Crossing Point Voltage at 0.7V Swing Vcross Variation over all edges Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Input to output skew in PLL mode Measured SE Measured at crossing point VOX Description Measured SE Condition Min. -150 250 - - - 0.2 - 2.5 Max. - 550 140 VHIGH + 0.3 -0.3 N/A 250 6.5 Unit mv mv mV V V V ps ns
tPD(NONPLL) Input to output skew in Non-PLL mode Measured at crossing point VOX
33 4 9 .9 33 4 9 .9
D IF T
T PCB
M e a s u re m e n t P o in t
2pF
D IF C IR E F
475
T PCB
M e a s u re m e n t P o in t
2pF
T r a c e Im p e d a n c e M e a s u r e d D if f e r e n tia lly
Figure 8. Differential Clock Termination
Switching Waveforms
TRise (CLOCK) VOH = 0.525V
CL OC K#
K OC CL
VCROSS
VOL = 0.175V
TFall (CLOCK)
Figure 9. Single-Ended Measurement Points for TRise and TFall
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CY28401
VOVS
VRB
VRB VLOW VUDS
Figure 10. Single-ended Measurement Points for VOVS,VUDS and VRB
TPERIOD
Skew Management Point
High Duty Cycle %
Low Duty Cycle %
0.000V
Figure 11. Differential (Clock-CLock#) Measurement Points (Tperiod, Duty Cycle and Jitter)
Ordering Information
Ordering Code CY28401OC CY28401OCT Lead-Free CY28401OXC CY28401OXCT 48-pin SSOP 48-pin SSOP-Tape and Reel Commercial, 0C to 70 C Commercial, 0C to 70 C Package Type 48-pin SSOP 48-pin SSOP-Tape and Reel Operating Range Commercial, 0C to 70 C Commercial, 0C to 70 C
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CY28401
Package Drawing and Dimensions
48-Lead Shrunk Small Outline Package O48
51-85061-*C
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28401
Document History Page
Document Title: CY28401 100-MHz Differential Buffer for PCI Express and SATA Document Number: 38-07592 Rev. ** *A ECN No. 130191 387766 Issue Date 11/26/03 See ECN Orig. of Change IJA/SDR RGL New Data Sheet Added Lead-free Description of Change
Document #: 38-07592 Rev. *A
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